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The functionality of devices could be changed simply by changing nanomaterials without impacting the processFour years ago, IBM announced that it was investing US $3 billion over the next five years into the future of nanoelectronics with a broad project it dubbed “7nm and Beyond.” With at least one major chipmaker, GlobalFoundries, hitting the wall at the 7-nm node, IBM is forging ahead, using graphene to deposit nanomaterials in predefined locations without chemical contamination.  In research described in the journal Nature Communications, the IBM researchers for the first time electrified graphene so that it helps to deposit nanomaterials with 97% accuracy.  “As this method works for a wide variety of nanomaterials, we envision integrated devices with functionalities that represent the unique physical properties of the nanomaterial,” said Mathias Steiner, manager at IBM Research-Brazil. “We also can envision on-chip light detectors and emitters operating within a distinct wavelength range determined by the optical properties of the nanomaterial.” As an example, Steiner explained that if you wanted to modify the spectral performance of an optoelectronic device, you could simply replace the nanomaterial while keeping the manufacturing process flow the same. If you take the method one step further, you could assemble different nanomaterials in different places doing multiple passes of assembly to create on-chip light detectors operating in different detection windows at the same time. The entire method can be considered a hybrid bottom-up/top-down process flow, according to Michael Engel, research staff member at IBM Research–Brazil. A couple of years ago, IBM created one of these hybrid processes that combined top-down manufacturing techniques—like lithography—with bottom-up techniques that “grow” electronics through self-assembly. Engel explained that the first step of this hybrid process involves growing graphene directly on top of the substrate where the nanomaterial assembly is performed. In IBM’s demonstration, they used graphene on silicon carbide. Engel noted that it is also possible to grow the graphene on another material, such as copper, then peel the graphene off and put it on a silicon/silicon oxide wafer. The next step was etching the graphene to define the deposition sites. This is done at a large scale and can be considered the top-down part of the process. The third step employs a bottom-up technique where researchers apply an AC electric field to the patterned graphene layers while depositing nanomaterial solution on top. The nanomaterial is then dragged down and trapped between opposing graphene electrodes. “So the graphene fulfills the function of defining the placement location and providing the electric field orientation and drag force for the directed nanomaterial assembly,” said Engel. In the fourth step of this process, the graphene deposition electrodes are etched away, followed by additional manufacturing steps for integrating and operating electronic or optoelectronic devices. The state of the art prior to this work was using metal electrodes, which are difficult to remove and limit device performance and integration potential. “We believe the biggest breakthrough of this work is the bottom-up placement of a wide variety of nanomaterials with nanometer-scale resolution over much larger, millimeter-scale areas with easily removable (residual free) electrodes,” said Steiner. “The graphene electrodes provide excellent nanomaterial alignment and density, limit chemical exposure, and avoid metal lines, enabling superior device performance.” This process is not going to come to the rescue of Moore’s Law overnight. One of the biggest challenges, according to Engel, is introducing solution-based nanomaterials into the industrial-scale manufacturing process. “This will require progress in the standardization of nanomaterial solutions to achieve repeatable and consistent results, as well as the adaption of the electric-field-assisted method for use in the wafer scale manufacturing processes,” said Engel. While standardization of nanomaterial solutions is not going to be solved by IBM, the researchers are continuing to work on the device level of the technology with the integration of different nanomaterials in order to customize basic integrated circuits such as, for example, electrical inverters or ring oscillators. Along these lines, the researchers are developing dedicated on-chip light emitters and detectors with spectral properties determined by the assembled nanomaterial. Editor’s Note: A small change was made on October 9th to correct the mistaken description that the graphene was peeled off of silicon carbide and put onto a silicon/silicon oxide wafer. These are actually two different embodiments of the method: either graphene is grown on silicon carbide (where it stays in place for further processing), or the graphene is grown on copper and transferred to the wafer for further processing.

Graphene-based remote epitaxy enables inexpensive copying of gallium arsenide and gallium nitride chipsFuture high-efficiency solar cells molded to the surface of a car, ultrasmall photonics chips, and low-power, long-lasting wearable devices will all require something no one’s yet been able to achieve, namely chips made from high-efficiency materials that are flexible, thin, and inexpensive to manufacture. A research group at MIT has announced a couple of developments in recent weeks that bring such a confluence of innovations closer to the achievable. Jeehwan Kim’s research group announced separately this month in Nature Materials and Science that they can inexpensively mass-produce ultrathin gallium arsenide and gallium nitride chips as well as harvest the monolayer materials necessary for manufacturing other 2D electronics, like tiny photonics devices. “We [found] the way to go to expensive semiconducting materials so you can keep producing high-quality, high-performance semiconductors with a cheaper price,” says Kim, associate professor of mechanical engineering and materials science at MIT. “The bonus is, you can have flexible semiconducting devices, and because they’re really thin, you can stack them up.” As IEEE Spectrum reported last year, Kim’s group essentially uses graphene sheets as nanosize silk screens through which expensively manufactured exotic-material-based semiconductors can be laid down. The recipe: Take a costly, manufactured, ultrathin film of pure semiconducting material like gallium arsenide and lay a single-layered sheet of graphene on top of it. Then flow atoms of gallium and arsenide over the graphene, and the intermediary sheet acts as a surface on which an identical copy of the underlying ultrathin film is copied on top of the graphene— although how and why the process worked as well as it did had previously been unclear. In the current work, Kim’s group has expanded and generalized their previous finding—discovering, on one hand, single-atom crystals like silicon cannot be replicated by the “silk screen” technique (what the group calls remote epitaxy) but on the other hand that practically any 2D sheet or film whose molecules carry any net electric polarity to them can be mass-produced via remote epitaxy. The reason, the group discovered, is that electrically the graphene behaves as if it’s not even there, transmitting the ionic electric fields from the 2D material up to the slurry of raw materials resting on top of the graphene. The fields then guide the slurry into forming a perfect duplicate of the expensively manufactured thin film below. Kim uses the shorthand term “copy-paste” to describe the simple and seemingly inexpensive procedure as it’s now being developed. (He admits, however, he cannot give price quotes at the moment, because they haven’t yet done an economic analysis of the process.) “We were able to copy-paste…through graphene for many types of compound materials in the periodic table,” says Kim. “That is a big discovery. Based on that understanding, we were able to make single-crystalline, freestanding, very, very thin membrane compound materials.” Kim says his research group is working with “six major companies” in Korea, Japan, and the United States to scale up the ultrathin chip manufacturing processes they’re developing. He expects some of these technologies might only need “a couple years” before they’re potentially ready for commercial application. The industries and product lines Kim says could find use for the remote epitaxy process include solar energy (cheap but ultra-efficient GaAs solar panels have long been a dream), photonics (layering multiple ultrathin films on top of each other, say, so that each are efficient at transmitting red LED light and blue LED light), wearables (making electronics ultraflexible but also low power is a holy grail in the field), and IoT (ditto). The group has a portfolio of published results that includes the graphene remote epitaxy process. Also in the running is another 2D material manufacturing technique, the one published in Science. “We developed a way to handle wafer-scale two-dimensional materials with atomic precision,” Kim says. The idea is that other materials that could be useful as conductors, insulators, and semiconductors may not necessarily work with the graphene method. In which case, Kim’s group has a second method for peeling off individual atom-thick monolayers. As they spell out in the Science paper, they discovered that other ultrathin films that may for various reasons not work as well with remote epitaxy could still be copied in another way. Compounds like hexagonal boron nitride (attractive as a lubricant, electrical insulator, or light emitter) and tungsten disulfide (another possible post-silicon solar panel material) can be flaked off into single-atom-thick sheets with a process Kim’s lab calls “controlled crack propagation.” The process involves growing a thick material on a wafer and then attaching the top of that material to a nickel plate. (2D films adhere more strongly to nickel.) The nickel plate can then be pulled up, in the process exfoliating a single-atom-thick layer of the target material. The exfoliated 2D film can then be laid down onto a host wafer as part of that wafer’s manufacturing process. Arbitrarily, many single-atom-thick layers can be laid down this way, Kim says, leading to new kinds of electronic devices that demand complex semiconducting substrates. “There has been no way of handling this one-atom-thick layer controllably,” Kim says. “That’s why industry has not been discussing using 2D materials in next-generation electronics. [But] we can just grow thick 2D material on the wafer. Then we just peel off one monolayer, then one monolayer. We can harvest a lot of 2D materials from…the wafer.” Between remote epitaxy and controlled crack propagation, Kim says many more flexible and efficient electronic, photonic, and other thin-film-based technologies can now be more reliably mass-produced.

Productivity gains will continue through the next two or three chip generations, but after that we’ll need something bigger and betterASML vice president Anthony Yen says that ASML has begun development of the extreme ultraviolet lithography machine his company believes will be needed to continue shrinking the features of silicon chips once today’s systems reach their limits. The ASML 5000 will rely on a number of evolutionary improvements over the 3400 series, which customers such as Intel, Samsung, and TSMC are using now. The most noticeable will be an increase in the machine’s numerical aperture from today’s 0.33 to 0.55, Yen told engineers at the IEEE International Electron Device Meeting this week in San Francisco.  Numerical aperture is a dimensionless quantity related to how tightly light can be focused. A higher numerical aperture means better resolution. Changing the numerical aperture in the EUV machine will require a larger, more perfectly polished set of imaging mirrors. EUV light is generated by targeting tiny tin droplets with twin pulses from a high-powered carbon dioxide laser. The first pulse reshapes the tin droplet into a hazy pancake shape so that the second pulse, which is more powerful and follows it by just 3 microseconds, can blast the tin into a plasma that shines with 13.5-nanometer light. The light is then collected, focused, and bounced off a patterned mask so that the pattern will be projected onto the silicon wafer. ASML has increased the number of wafers its machines can process per hour largely by generating more light power. More power means the wafer can be exposed more quickly. At 195 watts they could do 125 wafers per hour; they reached 246 W and 140 wafers per hour early this year. The company has been retrofitting customer machines throughout the year to hit that higher mark. A next-generation machine will need even more EUV wattage. In the lab, ASML has cracked 410 W, though not yet at a duty cycle good enough for chip production. More powerful lasers will help, and so might increasing the rate at which the tin droplets are zapped. In today’s machines, the tin drops are shot out 50,000 times per second, but Yen showed that the droplet generator could run at 80,000 hertz.   In the meantime, the company is improving the capabilities of its 3400 series. A new version, the 3400C, will be released in the second half of 2019 and surpass 170 wafers per hour. One sore spot in its development had to do with the extremely expensive masks that hold the pattern to be cast onto the silicon. The coverings, called pellicles, which are meant to protect the masks from stray particles, absorbed too much light. ASML says existing pellicles transmit 83 percent of light. This reduces throughput to 116 wafers per hour. The goal is to improve transmission to 90 percent, says Yen. But ASML is also working to keep the inside of the machine even cleaner than it does now, so that customers can feel free to use masks without a pellicle. Yen says ASML expects to have shipped 18 machines by the end of 2018, and is planning to ship 30 in 2019. However, a fire at a supplier will delay some 2019 deliveries, the company said on Tuesday. ASML lost a prominent customer in August when GlobalFoundries pulled the plug on its 7-nanometer chip development. That move eliminated the need for the two EUV machines the company installed in 2017 and 2018.

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Smart watches, fitness trackers, smart garments, smart medical attachments, data gloves - the market for wearable electronics is quickly evolving beyond health care, fitness and wellness into infotainment, and commercial and industrial applications. A review investigates the contribution of nanomaterials in the field of wearables with a focus on actuators and sensors. It discusses current applications of nanomaterials in this field and touch upon the different materials and methods being used.

TSMC is the big winner, having made them bothAt an event today, Apple executives said that the new iPhone Xs and Xs Max will contain the first smartphone processor to be made using 7 nm manufacturing technology, the most advanced process node. Huawei made the same claim, to less fanfare, late last month and it’s unclear who really deserves the accolades. If anybody does, it’s TSMC, which manufactures both chips.  TSMC went into volume production with 7-nm tech in April, and rival Samsung is moving toward commercial 7-nm production later this year or in early 2019. GlobalFoundries recently abandoned its attempts to develop a 7 nm process, reasoning that the multibillion-dollar investment would never pay for itself. And Intel announced delays in its move to its next manufacturing technology, which it calls a 10-nm node but which may be equivalent to others’ 7-nm technology. Apple’s new A12 Bionic is made up of six CPU cores, four GPU cores, and an 8-core “neural engine” to handle machine learning tasks. According to Apple, the neural engine can perform 5 trillion operations per second—an eight-fold boost—and consumes one-tenth the energy of its previous incarnation. Of the CPU cores, two are designed for performance and are 15 percent faster than their predecessors. The other four are built for efficiency, with a 50 percent improvement on that metric. The system can decide which combination of the three types of cores will run a task most efficiently. Calling the A12 Bionic “an impressive feat,” VLSI Research analyst G. Dan Hutcheson says the chip “demonstrates that the attractiveness of staying on Moore’s Law has not diminished.” Huawei’s chip, the Kirin 980, was unveiled at the IFA 2018 in Berlin on 31 August. It packs 6.9 billion transistors onto a one-square-centimeter chip. The company says it’s the first chip to use processors based on Arm’s Cortex-A76, which is 75 percent more powerful and 58 percent more efficient compared to its predecessors the A73 and A75. It has 8 cores, two big, high-performance ones based on the A76, two middle-performance ones that are also A76s, and four smaller, high-efficiency cores based on a Cortex-A55 design. The system runs on a variation of Arm’s big.LITTLE architecture, in which immediate, intensive workloads are handled by the big processors while sustained background tasks are the job of the little ones. Kirin 980’s GPU component is called the Mali-G76, and it offers a 46 percent performance boost and a 178 percent efficiency improvement from the previous generation. The chip also has a dual-core neural processing unit that more than doubles the number of images it can recognize to 4,500 images per minute. The Kirin 980 debuts in Huawei’s Mate 20 on 16 October. The first new generation iPhones start to ship on 21 September. This post was corrected to show the right number of CPU cores and updated to include analyst comment and shipping dates.

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Focus Graphite Inc. is happy to announce that Grafoid has launched a new series of oxidized graphene products called GNOX™ across the globe. Highly customizable graphene products are...

After installing extreme-ultraviolet lithography, foundry finds it doesn’t have enough customers for itIn a major shift in strategy, GlobalFoundries is halting its development of next-generation chipmaking processes. It had planned to move to the so-called 7-nm node, then begin to use extreme-ultraviolet lithography (EUV) to make that process cheaper. From there, it planned to develop even more advanced lithography that would allow for 5- and 3-nanometer nodes. Despite having installed at least one EUV machine at its Fab 8 facility in Malta, N.Y., all those plans are now on indefinite hold, the company announced Monday.  The move leaves only three companies reaching for the highest rungs of the Moore’s Law ladder: Intel, Samsung, and TSMC. It’s a huge turnabout for GlobalFoundries. During a tour of Fab 8 last October, executives told IEEE Spectrum that 7-nm chips would be, at the very least, in limited production by the close of 2018. At the time, the company was completing installation of its first EUV lithography machine, a delicate and extremely expensive task. GlobalFoundries rationale for the move is that there are not enough customers that need bleeding-edge 7-nm processes to make it profitable. “While the leading edge gets most of the headlines, fewer customers can afford the transition to 7 nm and finer geometries,” said Samuel Wang, research vice president at Gartner, in a GlobalFoundries press release.  “The vast majority of today’s fabless customers are looking to get more value out of each technology generation to leverage the substantial investments required to design into each technology node,” explained GlobalFoundries CEO Tom Caulfield in a press release. “Essentially, these nodes are transitioning to design platforms serving multiple waves of applications, giving each node greater longevity. This industry dynamic has resulted in fewer fabless clients designing into the outer limits of Moore’s Law. We are shifting our resources and focus by doubling down on our investments in differentiated technologies across our entire portfolio that are most relevant to our clients in growing market segments.” (The dynamic Caulfield describes is something the U.S. Defense Advanced Research Agency is working to disrupt with its $1.5-billion Electronics Resurgence Initiative. Darpa’s partners are trying to collapse the cost of design and allow older process nodes to keep improving by using 3D technology.) Specifically, GlobalFoundries is doubling down on chips made using it’s 14/12-nm FinFET process and plans to expand and develop the set of features offered at that node such as RF, embedded memory, low power, and other technologies. “Lifting the burden of investing at the leading edge will allow GF to make more targeted investments in technologies that really matter to the majority of chip designers in fast-growing markets such as RF, IoT, 5G, industrial, and automotive,” said Gartner’s Wang. Pressing pause on advanced manufacturing nodes was a wise move because it will improve GlobalFoundries financial prospects, according to VLSI Research analyst G. Dan Hutcheson. “If you’re a customer your biggest question is not just the technology but financially stability,” he says. Foundries “really have to have a path to profitability.”  GlobalFoundries isn’t the only company struggling with its crawl further down the Moore’s Law rabbit hole. Recently, Intel revealed that it was delaying its move to a 10-nm process until 2019. (Intel’s 10-nm process is thought to be roughly equivalent to others’ 7-nm processes.) That puts a yawning five-year gap between manufacturing nodes for the company.  The delay has allowed TSMC, which began offering 7-nm this year, to pass Intel. AMD, once GlobalFoundries’ biggest processor customer, has already been working with TSMC on 7-nm chips and—in line with GlobalFoundries plans—announced that it will focus “the breadth” its 7-nm resources there going forward. In a blog post Monday, AMD CTO Mark Papermaster wrote that the company’s first 7-nm GPU will come out later this year, and its first 7-nm server processor will launch in 2019. That would put AMD on a more advanced manufacturing node than Intel for the first time this century, notes ExtremeTech. Of the remaining three bleeding-edge manufacturers, only TSMC doesn’t compete directly with at least some potential customers. “It puts TSMC in a very unique position, and I’m sure they’ll leverage that,” says VLSI’s Hutcheson. The change at GlobalFoundries will involve layoffs among the staff at Malta. The number could be in the hundreds, according to The Albany Business Review.   This post was corrected on 18 September. Mark Papermaster is AMD’s CTO not it’s CEO. (That’s Lisa Su.)

Since the 2003 discovery of the single-atom-thick carbon material known as graphene, there has been significant interest in other types of 2-D materials as well. These materials could be stacked together like Lego bricks to form a range of devices with different functions, including operating as semiconductors. In this way, they could be used to create ultra-thin, flexible, transparent and wearable electronic devices. However, separating a bulk crystal material into 2-D flakes for use in electronics has proven difficult to do on a commercial scale. The existing process, in which individual flakes are split off from the bulk crystals by repeatedly stamping the crystals onto an adhesive tape, is unreliable and time-consuming, requiring many hours to harvest enough material and form a device. Now researchers in the Department of Mechanical Engineering at MIT have developed a technique to harvest 2-inch diameter wafers of 2-D material within just a few minutes. They can then be stacked together to form an electronic device within an hour. The technique, which they describe in a paper published in the journal Science, could open up the possibility of commercializing electronic devices based on a variety of 2-D materials, according to Jeehwan Kim, an associate professor in the Department of Mechanical Engineering, who led the research. The paper’s co-first authors were Sanghoon Bae, who was involved in flexible device fabrication, and Jaewoo Shim, who worked on the stacking of the 2-D material monolayers. Both are postdocs in Kim’s group. The paper’s co-authors also included students and postdocs from within Kim’s group, as well as collaborators at Georgia Tech, the University of Texas, Yonsei University in South Korea, and the University of Virginia. Sang-Hoon Bae, Jaewoo Shim, Wei Kong, and Doyoon Lee in Kim’s research group equally contributed to this work.  “We have shown that we can do monolayer-by-monolayer isolation of 2-D materials at the wafer scale,” Kim says. “Secondly, we have demonstrated a way to easily stack up these wafer-scale monolayers of 2-D material.” The researchers first grew a thick stack of 2-D material on top of a sapphire wafer. They then applied a 600-nanometer-thick nickel film to the top of the stack. Since 2-D materials adhere much more strongly to nickel than to sapphire, lifting off this film allowed the researchers to separate the entire stack from the wafer. What’s more, the adhesion between the nickel and the individual layers of 2-D material is also greater than that between each of the layers themselves. As a result, when a second nickel film was then added to the bottom of the stack, the researchers were able to peel off individual, single-atom thick monolayers of 2-D material. That is because peeling off the first nickel film generates cracks in the material that propagate right through to the bottom of the stack, Kim says. Once the first monolayer collected by the nickel film has been transferred to a substrate, the process can be repeated for each layer. “We use very simple mechanics, and by using this controlled crack propagation concept we are able to isolate monolayer 2-D material at the wafer scale,” he says. The universal technique can be used with a range of different 2-D materials, including hexagonal boron nitride, tungsten disulfide, and molybdenum disulfide. In this way it can be used to produce different types of monolayer 2-D materials, such as semiconductors, metals, and insulators, which can then be stacked together to form the 2-D heterostructures needed for an electronic device. “If you fabricate electronic and photonic devices using 2-D materials, the devices will be just a few monolayers thick,” Kim says. “They will be extremely flexible, and can be stamped on to anything,” he says. The process is fast and low-cost, making it suitable for commercial operations, he adds. The researchers have also demonstrated the technique by successfully fabricating arrays of field-effect transistors at the wafer scale, with a thickness of just a few atoms. “The work has a lot of potential to bring 2-D materials and their heterostructures towards real-world applications,” says Philip Kim, a professor of physics at Harvard University, who was not involved in the research. The researchers are now planning to apply the technique to develop a range of electronic devices, including a nonvolatile memory array and flexible devices that can be worn on the skin. They are also interested in applying the technique to develop devices for use in the “internet of things,” Kim says. “All you need to do is grow these thick 2-D materials, then isolate them in monolayers and stack them up. So it is extremely cheap — much cheaper than the existing semiconductor process. This means it will bring laboratory-level 2-D materials into manufacturing for commercialization,” Kim says. “That makes it perfect for IoT networks, because if you were to use conventional semiconductors for the sensing systems it would be expensive.”

Could nanotechnology tidy up the planet without leaving a dangerous residue of its own?It's likely that you've recently swirled nanotechnology down your sink. Antimicrobial silver nanoparticles, for example, are added to food containers, socks, and cleaning products such as floor polish. But could nanoparticles – measuring less than 100 nanometres wide – clean more than just your house? Could nanotechnology tidy up the planet without leaving a dangerous residue of its own?The European Environment Agency estimates that "potentially polluting activities" have occurred at nearly three million EU sites. But nanoparticles could remediate water, soil and air polluted by compounds such as heavy metals and aromatic hydrocarbons. With high reactivity and a larger surface area than the same mass of material in a larger form, nanoparticles are prime candidates for capturing and destroying pollutants. Continue reading...

NNT 2019, the 18th International Conference on Nanoimprint and Nanoprint Technologies (nnt2019.org), the world’s leading symposium

ConferenceMonday, October 14, 2019 to Wednesday, October 16, 2019Boston Seaport Hotel http://www.nnt2019.org/ NNT 2019, the 18th International Conference on Nanoimprint and Nanoprint Technologies, the world’s leading symposium on nanoimprint and nanoprint, will take place October 14-16, 2019, at The Boston Seaport Hotel, Boston Massachusetts, USA. NNT2019 is focused on Next Generation Technologies, Products and Manufacturing Processes and is structured with both the research and commercial communities in mind. The meeting will feature invited and contributed lectures on the latest developments in imprint technology. A series of plenary lectures from leading researchers within and external to the imprint community will focus on new and emerging areas in which imprint technology can expand and have significant commercial and scientific impact, including metamaterials, augmented and virtual reality, energy generation and storage, intelligent nanoscale devices and the life sciences. The conference will also offer a unique nanoimprint ecosystem session and roundtable discussion in which providers of tools, masters, materials and open access research and process development facilities will converge in a single session to provide a comprehensive look at potential commercialization paths for bringing product concepts from the laboratory to manufacturing. NNT 2019 will feature an extensive poster session describing recent science and technology advances as well as vendor exhibits from companies and institutes spanning the NIL ecosystem. An online portal for pre scheduling 1:1 meetings among conference participants, presenters in the ecosystem sessions and/or vendors will be provided to maximize opportunities for relationship building. Additional opportunities for networking and informal socializing will occur on a dinner cruise on the Boston Harbor. An optional post-conference tour to the $US 25 million Advanced Print and Roll-to-Roll Manufacturing Demonstration Facility at the University of Massachusetts Amherst will be arranged for those wishing to see facilities for implementation of the latest development in continuous imprinting technology and complementary processes for device integration and manufacturing. Register Now

ConferenceMonday, October 14, 2019 to Wednesday, October 16, 2019Boston Seaport Hotel http://www.nnt2019.org/ NNT 2019, the 18th International Conference on Nanoimprint and Nanoprint Technologies, the world’s leading symposium on nanoimprint and nanoprint, will take place October 14-16, 2019, at The Boston Seaport Hotel, Boston Massachusetts, USA. NNT2019 is focused on Next Generation Technologies, Products and Manufacturing Processes and is structured with both the research and commercial communities in mind. The meeting will feature invited and contributed lectures on the latest developments in imprint technology. A series of plenary lectures from leading researchers within and external to the imprint community will focus on new and emerging areas in which imprint technology can expand and have significant commercial and scientific impact, including metamaterials, augmented and virtual reality, energy generation and storage, intelligent nanoscale devices and the life sciences. The conference will also offer a unique nanoimprint ecosystem session and roundtable discussion in which providers of tools, masters, materials and open access research and process development facilities will converge in a single session to provide a comprehensive look at potential commercialization paths for bringing product concepts from the laboratory to manufacturing. NNT 2019 will feature an extensive poster session describing recent science and technology advances as well as vendor exhibits from companies and institutes spanning the NIL ecosystem. An online portal for pre scheduling 1:1 meetings among conference participants, presenters in the ecosystem sessions and/or vendors will be provided to maximize opportunities for relationship building. Additional opportunities for networking and informal socializing will occur on a dinner cruise on the Boston Harbor. An optional post-conference tour to the $US 25 million Advanced Print and Roll-to-Roll Manufacturing Demonstration Facility at the University of Massachusetts Amherst will be arranged for those wishing to see facilities for implementation of the latest development in continuous imprinting technology and complementary processes for device integration and manufacturing. Register Now

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180 Degree Capital Corp. (NASDAQ: TURN) will announce its first quarter 2019 financial results on Wednesday, May 1, 2019, shortly after the close of the public markets. It will host a conference call...

Graphene quantum dots drawn from common coal may be the basis for an effective antioxidant for people who suffer traumatic brain injuries, strokes or heart attacks.

Arrowhead Pharmaceuticals Inc. (NASDAQ: ARWR) today announced that it has begun dosing in a new triple combination cohort (cohort 12) that includes JNJ-3989 (formerly ARO-HBV) and additional undisclo...